JPS607566A - マルチプロセツサ・デ−タ処理装置 - Google Patents
マルチプロセツサ・デ−タ処理装置Info
- Publication number
- JPS607566A JPS607566A JP11488183A JP11488183A JPS607566A JP S607566 A JPS607566 A JP S607566A JP 11488183 A JP11488183 A JP 11488183A JP 11488183 A JP11488183 A JP 11488183A JP S607566 A JPS607566 A JP S607566A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- cpu
- data
- resource
- resource section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11488183A JPS607566A (ja) | 1983-06-25 | 1983-06-25 | マルチプロセツサ・デ−タ処理装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11488183A JPS607566A (ja) | 1983-06-25 | 1983-06-25 | マルチプロセツサ・デ−タ処理装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS607566A true JPS607566A (ja) | 1985-01-16 |
JPH0133865B2 JPH0133865B2 (en]) | 1989-07-17 |
Family
ID=14649011
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11488183A Granted JPS607566A (ja) | 1983-06-25 | 1983-06-25 | マルチプロセツサ・デ−タ処理装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS607566A (en]) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54136151A (en) * | 1978-04-13 | 1979-10-23 | Sumitomo Electric Ind Ltd | Multiple microprocessor |
JPS5622160A (en) * | 1979-07-31 | 1981-03-02 | Fujitsu Ltd | Data processing system having additional processor |
-
1983
- 1983-06-25 JP JP11488183A patent/JPS607566A/ja active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54136151A (en) * | 1978-04-13 | 1979-10-23 | Sumitomo Electric Ind Ltd | Multiple microprocessor |
JPS5622160A (en) * | 1979-07-31 | 1981-03-02 | Fujitsu Ltd | Data processing system having additional processor |
Also Published As
Publication number | Publication date |
---|---|
JPH0133865B2 (en]) | 1989-07-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP3039540B1 (en) | Virtual machine monitor configured to support latency sensitive virtual machines | |
US5187802A (en) | Virtual machine system with vitual machine resetting store indicating that virtual machine processed interrupt without virtual machine control program intervention | |
US5706514A (en) | Distributed execution of mode mismatched commands in multiprocessor computer systems | |
US5218712A (en) | Providing a data processor with a user-mode accessible mode of operations in which the processor performs processing operations without interruption | |
CA2009529C (en) | Servicing interrupt requests in a data processing system without using the services of an operating system | |
US4484271A (en) | Microprogrammed system having hardware interrupt apparatus | |
JPS5841538B2 (ja) | マルチプロセツサシステム ノ ユウセンセイギヨホウシキ | |
WO1994003860A1 (en) | Massively parallel computer including auxiliary vector processor | |
JPH0430053B2 (en]) | ||
JPH0689269A (ja) | プロセッサの制御装置、プロセッサの休止装置およびそれらの方法 | |
EP0301707B1 (en) | Apparatus and method for providing an extended processing environment on nonmicrocoded data processing system | |
JPS607566A (ja) | マルチプロセツサ・デ−タ処理装置 | |
CA1302580C (en) | Apparatus and method for using lockout for synchronization of access to main memory signal groups in a multiprocessor data processing system | |
Maekawa et al. | Experimental polyprocessor system (EPOS)—Architecture | |
JPS6223895B2 (en]) | ||
JPH0290331A (ja) | 仮想計算機システムのためのプロセツサ間通信命令処理装置 | |
JPH0444131A (ja) | 複数os走行システムにおけるプロセッサ間通信の実行装置および方法 | |
JPS60229162A (ja) | 多重処理装置の制御方式 | |
Fuccio et al. | Hardware architecture considerations in the WE32100 chip set | |
JPH0628320A (ja) | マルチプロセッサシステム | |
JPS6143369A (ja) | マルチプロセツサシステム | |
JPS6210758A (ja) | プロセツサモジユ−ル | |
JPH05257909A (ja) | マルチプロセッサ内蔵1チップマイクロコンピュータ | |
JPH04348437A (ja) | デバッグ装置 | |
JPH04133155A (ja) | デイジタル計算機 |